1. Field of the Invention
The invention relates to a low-capacitance multilayer chip varistor, and more particularly, to a low-capacitance multilayer chip varistor having capacitance lower than 0.5 pF at 1 MHz for suppressing electrical overstress and electrostatic shock and protecting electronic circuits.
2. Description of the Related Art
The trend in electronic industry is towards higher working frequencies and smaller sizes. Therefore, the need of using varistors for protecting IC from damage due to electrical overstress is getting greater for high frequency application.
Conventional varistor is mainly composed of ZnO or SrTiO3, and completed by sintering after oxides are added. Take ZnO varistor as an example, it is composed of ZnO and oxides of Bi, Sb, Si, Co, Mn, Cr and so on. At the high temperature more than 1000° C., Bi2O3 and oxides of Co, Mn, Cr and so on form a grain boundary among ZnO particles which has a microstructure like a grain boundary barrier capacitor. Thus, varistor composed of such materials has higher capacitance ranging from tens of pF to thousands of pF. Even the above materials are used in multilayer chip varistor, the varistor capacitance ranges from about 3 pF to hundreds of pF at 1 MHz. In circuits for high frequencies, when capacitance of the component for providing protection exceeds 3 pF, signals will distort. Therefore, the above component for providing protection is not suitable for high frequencies circuits.
Similarly, varistor component composed of SrTiO3 has capacitance more than thousands of pF and is not suitable for circuits for high frequencies. In addition, when the transmission frequency is higher, the capacitance should be lower to prevent the signals from distortion.
U.S. Pat. No. 5,976,420 disclosed a chip type multilayer varistor having a low capacitance and high non-linearity coefficient, mainly composed of SiC containing at least two oxides selected from among SiO2, Bi2O3, PbO, B2O3 and ZnO in an amount of from 0.1 to 20 mol %, and then combined with toluene and a binder agent and mixed by using a ball mill to obtain slurries, and thereafter become ceramic green sheets by using a doctor blade process. A paste was printed on the surface of the green sheets to form an inner electrode thereon. A predetermined number of ceramic green sheets were stacked to form a layered body. The resultant layered body was bonded by pressing at a constant pressure. The resultant green compact was cut into small-sized chips. The green chip was baked at a temperature in the range from 700 to 1100° C. to complete a ceramic multilayer chip type varistor resisting electrostatic shock and having surge voltage suppressing capability and a high non-linear coefficient from 10 to 20. The chip has a capacitance in the range from 10 to 40 pF, though not quite high, being much greater than 3 pF, and thus not suitable for using in high frequency circuits.
U.S. Pat. No. 6,251,513 disclosed a component for providing protection. Materials of the component comprise conductive and semi-conductive particles having a particle size of less than 10 μm and they are mixed with a polymer insulating binder to become a paste-like material. Left and right conductive electrodes are printed on a same surface of an insulating substrate and the paste-like material is filled in the gap between two conductive electrodes and then baked. Although the capacitance thereof is low and smaller than 0.25 pF at 1 MHz, the component is suitable for providing protection for high frequencies circuits. The insulating material is composed of polymer material, it is meant that heat generated by electrostatic shock or surge electrical overstress will carbonize the polymer material, make the component to be conductive and lose protection effect for electronic circuits or components. Thus, this component will not have good electrostatic shock withstanding capability and the lifetime thereof is short. Failure will occur only after 500 times of electrostatic shock when static electricity of direct contact 8 KV is applied.